On-chip resistor and capacitor elements are used in many circuit applications. For example, capacitor elements can be used in internal and peripheral circuitry, and Electrostatic Discharge (ESD) networks. Peripheral circuits of semiconductor chips use capacitors for coupling and de-coupling of drivers, receivers, and power busses.
Decoupling capacitors are used on peripheral circuit power busses for noise stabilization, dampening and other applications. Standard decoupling capacitors are implemented into advanced semiconductor chips between the power rails for the standard power supply voltage "Vdd" and the substrate ground potential "Vss," in order to reduce noise when a chip is in operation. This capacitance is added using normal thin oxide devices with heavily doped silicon gate structures. Decoupling capacitor networks are provided with control circuitry to enable and disable capacitor structures. Decoupling capacitors have been applied with fuse elements, an electronic switch (B. Krauter et al., U.S. Pat. No. 5,506,457) and other circuit implementations.
Polysilicon-to-silicon capacitors are typically placed over a heavily doped implanted silicon region. Polysilicon-to-silicon capacitors are also designed over well structures. Capacitors can consist of a gate structure placed on a well or a substrate region. U.S. Pat. No. 4,914,546 (hereafter "Alter") shows a heavily doped polysilicon gate structure over an n+ diffusion implant. Additionally, Alter shows that a heavily doped polysilicon film may be placed over a second heavily doped polysilicon film to construct a polysilicon-to-polysilicon capacitor.
U.S. Pat. No. 4,167,018 to Ohba et al. shows a heavily doped polysilicon gate structure over a well, wherein the well is placed in a substrate. U.S. Pat. No. 4,914,497 to Kondo provides an MIS capacitor using an oxidation resist film as a dielectric material on a doped region. U.S. Pat. No. 5,244,825 to Coleman et al. Shows a heavily doped polysilicon gate structure over an n+ diffusion implant. Additionally, Coleman et al. show that a heavily doped polysilicon film can be placed over a second heavily doped polysilicon film to construct a polysilicon-to-polysilicon capacitor.
As gate oxide films scale to thinner dielectric films, the dielectric becomes less tolerant of overvoltage conditions. Oxide breakdown, measured by the charge-to-breakdown, decreases with dielectric scaling. Inter-dielectric film thicknesses are also decreasing, making circuitry more sensitive to voltage stressing, and electrical overstress (EOS) and electrostatic discharge (ESD) phenomena. This is a concern in metal oxide semiconductor field effect transistor (MOSFET) structures which must interface with voltages above the native voltage of the semiconductor process.
Overvoltage conditions are of particular concern in decoupling capacitors placed on the Input/Output (I/O) power rail.